this product is covered under multiple patents held or licensed by comtech aha corporation. this product is covered by a turbo code patent license from france telecom - tdf - groupe des ecoles des telecommunications. comtech aha corporation comtech aha corporation product brief AHA4524 (4 kbit block version) turbo product code encoder/decoder the AHA4524 device is a single-chip turbo product code (tpc) fo rward error correction (fec) encoder/decoder. this device integrates independent tpc encoder and decoder functions, and can be configured for full or half duplex operation. in addition to tpc coding, the device includes helical interleaving, crc computation, and data scrambling. each of the functional blocks can be independently bypassed. figure 1 shows the functional block diagram. the encoder and decoder accept data and configuration through a synchronous 3-wire or data bus interface designed to co nnect directly to a dsp or user logic. encoder and decoder configuration registers are written and read through th e same interface as the data. configuration registers may be accessed at the start of every block transfer. the encode datapa th, with all functional blocks enabled, computes and in serts crc bits, scrambles the data, inserts error co rrection code (ecc) bits, and helically interleave s the data. the decoder datapath is the reverse of the encoder datapath. with all functional blocks enabled, the received data is helically deinterleaved before decoding. the decoder output is desc rambled, and the crc is computed to verify data integrity. decoded data is then output in a serial bit stream. the decoder input interf ace includes an option to accept 4 bit parallel soft metric data symbols. the parallel decoder input is used to support a symbol per transfer for fast channel input rates. the AHA4524 also includes fast code changing feature which allows the device to process multiple block types simultaneously. features performance: ? 60 mbit/sec channel rate and 50 mbit/sec payload data rate for (64,57)x (64,57) code with 3 iterations integrated 16 bit scrambler and descrambler integrated 32 bit crc computation and verification supports two dimensional (2d) and three dimensional (3d) turbo product codes supports 2d enhanced turbo product codes correction count for channel snr estimation simultaneously processes multiple block types flexibility: code rates from 0.25 to 0.97 encoded block sizes from 64 bits to 4 kbits programmable code shortening supports exact block sizes programmable decoder in put quantization for up to 4 bit wide soft metrics programmable iterations up to 255 per block 4 programmable block configurations which are selectable for fast code changing on chip pll allows low frequency system clock channel interface: synchronous 3-wire input and output ports designed to be compatib le with dsp serial ports bus mode input and output ports designed to be compatible with a dsp bus chip selects on encoder and decoder ports for full or half-duplex operation pin selectable interface control signal polarity decoder supports 4 bit pa rallel soft metric input data for fast decode operation system interface: secondary input communi cation cycles are used for accessing the AHA4524 configuration registers through the data ports block status is optionally output at the end of every decoded block to provide correction and crc error information electrical: 3.3v i/o, 1.8v core operation 5v tolerant inputs ttl signal compatible 64 pin tqfp package commercial or industrial temperature rating
comtech aha corporation figure 1: AHA4524 functional block diagram system application figure 2 is a block diagram of a wireless system that shows AHA4524 being used as a tpc encoder/decoder. during decoding, data is routed between the analog front end (afe) and asic/dsp through a serial port. the data is then processed in the asic/dsp to block and prepare the data for the AHA4524 decoder. data blocks are then transferred to the aha4 524 for tpc decoding. data received from AHA4524 is then routed to memory/peripheral functions. encoding is done in a similar manner where the ecc bits are added to the block of data. the encoded data block is further processed for modulation and frame synchronization as requ ired, then transmitted. figure 2: system block diag ram, wireless communication c_data descrambler AHA4524 decoder crc verification etpc decoder d_data configuration registers helical deinterleaver u_data encoder e_data i/o formatter scrambler helical interleaver etpc encoder configuration registers crc computation i/o formatter transmit AHA4524 (encoder) asic / dsp memory / peripheral analog front end (afe) AHA4524 (decoder) asic / dsp memory / peripheral
comtech aha corporation code performance table 1 gives an abridged list of possible codes su pported by AHA4524, along with the code rate and coding gain of each code. this is a very small subset of supported codes. aha can provide software to assist the code selection process. table 1: partial code list and performance * estimated coding gain is measured on a binary input additive white gaussian noise (awgn) channel at 10 -6 bit error rate (ber) and 3 iterations. + enhanced tpc (includes hyper axis ). in enhanced codes, the y axis is shorte ned by one. the shortening and addition of hyper axis is included in the code description. figure 3: comparison of tpc code types code (x)x(y)x(z) block size (bits) data size (bits) rate coding gain* (db) max channel rate at 3 iterations (mb/s) (64,63)x(64,62)+ 4096 3906 0.954 4.4 39.2 (64,57)x(64,62)+ 4096 3534 0.863 5.8 39.2 (64,57)x(64,57) 4096 3249 0.793 6.7 60.0 (32,26)x(32,26)x(4,3) 4096 2028 0.495 7.3 40.8 t pc @ 3 iterations 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 012345678910 eb/no (db) bit error rate p(e) uncoded bpsk rs(255,239) r=.937 tpc(64,63)x(64,62)+ r=.954 tpc(64,57)x(64,62)+ r=.863 tpc(64,57)^2 r=.793 tpc(32,26)x(32,26)x(4,3 ) r=.495
comtech aha corporation pb4524_0204 ? 2005 comtech aha corp. comtech aha corporation 1126 alturas drive fax: 208.892.5601 tel: 208.892.5600 e-mail: sales@aha.com www.aha.com moscow, id 83843-8331 a subsidiary of comtech te lecommunications corporation figure 4: tpc performance wi th 3, 8 and 32 iterations about aha comtech aha corporation (aha) develops and markets superior integrated circuits, boards, and intellectual property core technology for communications systems architects worldwide. aha has been setting the standard in forward error correction and lossless data compression technology for many years and provides flexible, cost-effective solutions for today?s growing bandwidth and reliabilit y challenges. comtech aha corporation is a wholly owned subsidiary of comtech telecommunca tions corp. (nasdaq: cmtl). for more information, visit www.aha.com. ordering information t pc (64,57)^2, rate 0.793 @ 3, 8, and 32 iterations 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 0123456 eb/no (db) bit error rate p(e) uncoded bpsk tpc(64,57)^2, 3 iter tpc (64,57)^2, 8 iter tpc(64,57)^2, 32 iter part number description AHA4524a-031 ptc 4 kbit block tpc encoder/ decoder - commercial temp AHA4524a-031 pti 4 kbit block tpc encoder/ decoder - industrial temp
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